An Integrated circuit (IC) is tested to verify whether it functions properly. An IC can be tested in order to detect its defects, some of which may have been introduced from process variations when being manufactured. Testing may include two verification stages, e.g., functional verification and connectivity verification. The functional verification stage may be used to determine whether the IC is capable of functioning in its intended manner.
However, the connectivity verification determines whether interconnections within the IC or between ICs provide proper electrical connection. Typical connectivity verification utilizes boundary scan test method. The boundary scan test method verifies connectivity between interconnects on a printed circuit board (PCB) or between circuit blocks within the IC without using a physical test probe. The boundary scan testing can be implemented with design-for-test (DFT) circuitry such as, scan cells and Joint Test Action Group (JTAG) Test Access Port (TAP) controller.
However, applying boundary scan testing on the transceiver, which includes many interconnections that may need connectivity verification, can be challenging because of high frequency signal propagation within the transceiver. Furthermore, it is known that boundary scan registers built within the transceiver may compromise signal integrity when performing the boundary scan testing.
It is within this context that the embodiments described herein arise.